1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of replacing an anti-punch through implant and a pocket implant with a single delta-channel implant in the fabrication of integrated circuits.
2. Description of the Prior Art
In scaling down semiconductor devices to the deep sub-micron regime, higher doped channels are required for short channel devices. Normally, an anti-punch through implant and a large angle pocket implant are made into the channel region before gate oxidation. The anti-punch through implant inhibits source/drain leakage and the pocket implant suppresses drain induced barrier lowering (DIBL) of the anti-punch through implant. However, the increased channel doping will also increase junction capacitance, junction leakage, and reverse short-channel effect. It is desired to suppress short-channel effect without increasing junction capacitance and leakage.
A number of U.S. Patents teach various methods of LDD and anti-punch through implants. U.S. Pat. No. 5,766,998 to Tseng discloses a polysilicon masking layer with spacers and two ion implants--for punch through and threshold voltage adjustment. U.S. Pat. No. 5,538,913 to Hong teaches an anti-punch through implant masked by conducting spacers which become part of the gate. U.S. Pat. No. 5,434,093 to Chau teaches an anti-punch through implant using oxide spacers as a mask. The oxide spacers remain. U.S. Pat. No. 5,698,461 to Liu also teaches an anti-punch through implant. U.S. Pat. No. 5,429,956 to Shell et al teaches an anti-punch through implant through polysilicon narrowed by oxide spacers. U.S. Pat. No. 5, 677,218 to Tseng shows an ion implant through a mask and polysilicon layer.